搜索资源列表
ram
- verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
fifo-ram
- 采用Verilog语言描述的FIFO和双端口RAM源代码。
ram
- RAM， Random-access memory，Verilog code
verilog编写的ram
- verilog编写的ram
dual_ram
- FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
dual_port_ram
- 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
VGA
- 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
spmem.tar
- Sinlge port RAM VHDL/Verilog design
ram_dp_sr_sw
- dual ram port in verilog
ram-rom-VerilogHDL
- 利用Verilog编写的各种RAM ROM的代码以及他们的测试模块-Prepared using a variety of RAM ROM Verilog code and their test module
Single-port-RAM-
- 单口RAM带CLR信号的verilog程序。很详细的.-Single-port RAM with a CLR signal
AHB_slave-ram
- AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
RAM_BLOCK
- Ram block code in Verilog
一种arm7源码（Verilog）
- 一种arm7源码（verilog），arm7结构比较老了，不过用来初学还是不错的(A kind of ARM7 source code (Verilog))
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)